For More details: chethan@onssearch.in

Regards Chethan
9964831455

Location :Bangalore

Send your resumes with subject line “for NXP” to jobs@testbench.in

If you are Interested above mention job please send your updated resume to prathap@fusionservices.in

Thanks&Regards

Prathap Muppala,
Recruitment Specialist,
Fusion Intellect Services
Phone:+91 80 32488880

1. Full chip and module level verification.

2. Work closely with the RTL designers, System Architects and Firmware team to develop test-plan, testbench & test cases, and help debug the design issues. Evaluate and enhance test coverage.

3. Processor based SOC verification experience is a must.

4. Hands-on experience in writing ASM code.

5. Experience with PCI Express, SAS, DDR, ARM Processors, AMBA bus & high speed interfaces is a plus.

6. Strong programming skills in Verilog, System Verilog, C/C++

7. Hands-on scripting experience (TCL, Perl, Awk, Shell).

8. Strong debugging skills.

9. Candidate must be a self starter & self motivated.

10. Strong team work required.

11. Candidate must have worked on verification of several ASICs, which went into volume production.

12. Exposure to power verification flow, such as UPF is a plus.

Experience Required: 7 to 12 years
Education Required – BSEE / MSEE or equivalent

Please send resumes to jobs@plianttechnology.com

Amanda Lachapelle
Executive Recruiter
www.plianttechnology.com
630 Alder Drive, Suite 202 Milpitas, CA 95035
Office: 408-321-0320 Ext:160
Cell: 408-334-0142
*Recently selected to the number 5 spot on the Lead411 Technology 500 list of the fastest growing tech companies in the U.S. !!

Skills required : Verilog , System verilog, C,C++, PCIe protocol knowledge

Location: Bhubaneswar

If you are interested to relocate @ bhubaneswar and having above listed skills please send your latest CV to mihir.sah@gmail.com

Thanks and regards,

Mihir

The job description is below.

People with good knowledge of RTL verification, test bench development with at least 3-5 years of experience.
Working experience on 1-2 OVM based projects is a must.

This is an immediate requirement and salary will be as per industry standanrd for the deserving candidate.

Send resumes to niranjanmm yahoo com

Should have worked with ARM based designs which include DDR controllers (DDR1/2/3)

Minimum 2+ years of working experience with AXI, AHB and APB

Minimum 4+ years of verification experience with C/PLI based verification environments and/or High level verification languages like Specman using NCSIM simulator

Minimum 3+ years of RTL verification experience with Specman/HVL. Domain knowledge on design/verification of dynamic memory controllers (SDR, DDR, DDR2 and future technologies) is a MUST.

Must have ASIC design experience developing and verifying memory controller ASIC’s for SDRAM, DDR, QDR, burst/page and async NOR and NANDFLASH. The critical areas are SDRAM & DDR, plus extensive experience with interface characterization.

Responsibilities also include verification of ASIC at full chip level, develop detailed test plan and regression suites and be responsible for their implementation, run gate level timing simulations and work with design engineers to achieve complete coverage to get first working silicon.

Experienced in C/C++ with a thorough knowledge on object oriented programming will be a plus. Experience in writing BFMs, cycle/transaction-accurate modeling is a must.

Working experience with high speed serial interfaces like USB 2.0, SATA, PCI-express will be a plus.

Should be skilled at isolating and identifying design bugs

Broad understanding of RTL-to-Tapeout methodology

Working knowledge of csh/perl scripting

Must be a good team player

Nice to have:

Experience with other on-chip buses like OCP is a plus

Experience with Verilog/PSL/OVA assertions is a plus

Experience with developing BFMs for stimulus generation, checking and bus monitors is a plus

Prior experience in working with remote teams is a plus

Location: Hyderabad

If interested Pls share your updated profile to purvi@mindsoftconsulting.com

Job Requirement:

· MSEE with 10+ years or BS with 12+ years in chip design and verification.

· Experience in managing 2 to 5 engineers.

· Worked in the US or a US based company in India for 5+ years.

· Should have worked as an individual contributor in an ASIC verification background for 5 years.

· Experience in verification lead position.

· Experience in planning the verification process, resource allocation and creating realistic schedule estimates.

· Experience in developing coverage-driven verification test plans.

· Experience writing test specifications (plans) and creating directed and random test cases.

· Experience managing regression analysis

· Experience in high level Object Oriented test bench environments such as VMM/UVM .

· Strong System Verilog, PERL, TCL, and C/C++ programming skills

· Experience in planning the verification process and coming up with realistic schedule estimates.

· Able to adopt the use of new techniques and methodologies and promote their use within the project.

· A high level of pro-activity, initiative and problem solving.

· Familiarity with constrained random and assertion based verification is preferred

· Verification experience in SERDES, Ethernet Networking in Verilog is a big plus.

· Knowledge of SONET and IEEE 802.3 Physical layer clauses is a plus.

2. Sr Verification Engineers Req

Job Requirement:

· MSEE with 10+ years or BS with 12+ years in chip design and verification.

· Worked in the US or a US based company in India for 5+ years.

· Should have worked as an individual contributor in an ASIC verification background for 5 years.

· Experience in verification lead position.

· Experience in planning the verification process and creating realistic schedule estimates.

· Experience in developing coverage-driven verification test plans

· Experience writing test specifications (plans) and creating directed and random test cases.

· Experience managing regression analysis

· Experience in high level Object Oriented test bench environments such as VMM/UVM .

· Strong System Verilog, PERL, TCL, and C/C++ programming skills

· Experience in planning the verification process and coming up with realistic schedule estimates.

· Able to adopt the use of new techniques and methodologies and promote their use within the project.

· A high level of pro-activity, initiative and problem solving.

· Familiarity with constrained random and assertion based verification is preferred

· Verification experience in SERDES, Ethernet Networking in Verilog is a big plus.

· Knowledge of SONET and IEEE 802.3 Physical layer clauses is a plus.

For more information: jabeena.m@alpconsulting.in
Mobile: 9538716955

Job Responsibilities:
Be an integral part of a team that is developing checkers and protocol monitors, such as PCI Express and 10 Gigabit Ethernet, for use with 0-In’s advanced functional verification tools and Questa RTL simulation.
0-In’s checkers and monitors help design teams find more bugs in less time
than conventional simulation techniques.
You will specify, implement, test, and manage regression tests for standard checkers and protocol monitors for a wide range of end user applications, as well as custom checkers and monitors for specific customers. You will interact with TMEs and CSDs or directly with customers to resolve customer issues.

Job Requirements:
• Solid Verilog HDL RTL knowledge
• Solid RTL simulation and test bench experience
• Intimate knowledge of one or more standard bus protocols
• Solid engineering
• B.Tech/M.Tech in electrical engineering or related field
• 1-3 years of experience in verification engineering

Desired Requirements:
• Experience with cycle-based simulation and constrained-random simulation
• Knowledge of assertion languages or libraries, such as PSL, SVA, OVL
• VHDL & System Verilog HDL RTL knowledge
• Experience with System C or C++
• Experience with Specman Elite or Vera/NTB
• Experience with Formal Property Verification tools

Other Requirements:
Bus Protocol know how with SV, AVM, Vera, Specman knowhow etc.