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Application Engineering Consultant -Mentor Graphics Corporation

Posted by verification job on May 28, 2010

Mentor Graphics Corporation

Job Posting Title
Application Engineering Consultant / 50255740

Reference Code
50255740E

City
Bangalore

Job Requirements
• Assisting global customers deploy Mentor Graphics’ HDL-based design and Scalable Verification software to solve ASIC/FPGA design challenges.
• Supporting HDL-based design and functional verification software in pre-sales and post-sales situations, both on-site in global customers’ locations and from your office.
• Helping Global Account Managers determine sales execution strategy by identifying and qualifying the match-up between global customer needs and Mentor Graphics’ HDL-based design and Scalable Verification software products.
• Illustrating the value Mentor Graphics brings to global customers by:
o Troubleshooting technical obstacles to the deployment of Mentor Graphics’ HDL-based design and Scalable Verification software
o Developing and delivering software demonstrations and technical presentations;
• Communicating global customers’ technical requirements to product marketing;
• Assisting global customers with their software evaluations and benchmarks.
• Developing a network of technical relationships at a peer-to-peer level with global customers.
• Managing and coordinating the technical relationships between global customers, the Mentor Graphics’ Global Account team and product marketing.

Job Qualifications
• BE/BTech. with minimum 4 years on functional verification. At least one of the following:
1. Hands-on functional verification experience on large ASIC (2M+ gates).
2. Experience in a support/sales role on any functional verification tools technologies.
• Ideal candidates will also have two or more years of sales experience working in a high paced team sales environment, with strong communications and interpersonal skills
• Must have a conceptual understanding of VLSI Device verification.
• Should be willing to train the customer on-site.
• Excellent communication skills and people skills.
• Experience on PERL and shell scripts desired
• Experience with HDL-based, register-transfer-level (RTL), digital logic design, verification languages, and functional verification methodology, for ASICs and/or FPGAs. This experience should include some of the following: VHDL and Verilog HDL simulation, synthesis and static timing analysis plus Assertion-Based Verification, including familiarity with OVL assertions, SystemC, SystemVerilog and/or PSL.

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