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DV Synapse Design

Posted by verification job on August 31, 2010

DV Synapse Design p


Design Verification

Create verification plans for SoC level verification

Create testbenches in C/C++

Utilize advanced verification techniques

Write tools and scripts in Perl and other script languages to enhance the verification process

Qualifications and requirements:

BS, MS, PhD, in computer science or engineering

Working knowledge of ARM-based processors and AMBA bus protocols

Experience with simulators from one or more of the major EDA suppliers (Cadence, Mentor or Synopsys)

Working knowledge of Verilog

Experience with tools for regression management, configuration management and bug tracking

Good problem solving and debugging skills

Qualifications: BS or MS

Experience: 4 to 12 yrs


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