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Archive for August, 2010

ASIC Design-Verification lead (DVL-08-01)

Posted by verification job on August 19, 2010

Job code: DVL-08-01

Exp: 4-8 years

Note: there are also individual contributor roles. Summary of skills needed:

– Advanced verification methodologies, preferably SystemVerilog – including testbench development
– (G)DDR2/3 verification experience
– Good problem solving, teamwork

Send CV to career@cvcblr.com
———-

As an ASIC Verification engineer at high end semiconductor design house, verify the design and
implementation of the industry’s leading Graphics and Video
Processors. Specific areas include 2D and 3D graphics, mpeg, video,
audio, high-speed IO interfaces and bus protocols, and memory
subsystem design. In this position, you will be responsible for
verification of the ASIC design – architecture and micro-architecture
– and it may include pre-silicon, emulation, and post-silicon
activities. You are expected to understand the design and
implementation, define the verification scope, develop the
verification infrastructure and verify the correctness of the design.
You will be working with architects, designers, pre and post silicon
verification teams to accomplish your tasks.

Requirements:
Exposure to design and verification tools (VCS or equivalent
simulation tools, debug tools like Debussy)
Good debugging and problem solving skills. Scripting knowledge
Expertise in SystemVerilog or similar HVL
C/C++ programming language experience desirable
Experience in architecting test bench environments for unit and system
level verification
Experience in verification using random stimulus along with functional
coverage and assertion-based verification methodologies
Good communication skills and ability & desire to work as a team
player are a must
Qualification:
BS / MS with 8+ years of experience

From http://www.cvcblr.com/blog/?p=193

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Exp: 4 – 7 Years Work Location: Bangalore/Hyderabad.

Posted by verification job on August 18, 2010

Hi
we are looking out very good professional : Skill Set: VLSI
(System Verilog, SoC Verification, Verilog, VHDL)
Exp: 4 – 7 Years
Work Location: Bangalore/Hyderabad.
Company : CMM level 5
Drive Location: Hyderabad.
please send me the profiles : victor@formulahrc.com
Thaks
Victor Kumar

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Verification Engineers – HYD

Posted by verification job on August 17, 2010

Send resumes to jobs@testbench.in with subject “Verification Engineers – HYD”.

Opening is in HYDERABAD.
A Fabless Semiconductor Company.
Looking for 4-6 Exp in Verification.
Knowledge of PCI, USB, IEEE1394, Ethernet is needed.

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VERIFICATION (MULTIMEDIA CHIP)

Posted by verification job on August 17, 2010

Urgent requirement for experts (3-4 years) with the following experience:

Job Description: Verification of Multimedia chips.
Skills Required: System C, C, Verilog & Strong knowledge in Verification Concepts.

If interested, pls send your latest CV to maneshm@mirafra.com

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Verification(system verilog/specman) requirement openings in large semicon, bangalore (8+yrs)

Posted by verification job on August 17, 2010

Requirement 1

Implement verification plans to verify unit level, sub-system and core / chip level functionality. Define, architect and build a robust and
re-usable verification environment for the core / chip.Solid understanding
of VHDL / Verilog based RTL designs. Verification coding experience in
System Verilog with OVM knowledge with good debugging expertize. Work closely with design engineers to ensure adequate functional and code coverage, and create fully random based testbench and testcases. Preference given to candidates with formal verification experience. BTech, M Tech/MS with minimum 8+years experience (atleast 3 yrs in a leadership role). 2 years
experience with System Verilog / Vera / Specman Constrained Random test-bench knowledge.1 year experience with Assertion-Based Verification (SVA, PSL).
Excellent communication skills and ability to work with a global team

Requirement 2

Brief Job Description: Experience in presilicon verification,
preferably processors or north bridges .Skills include test writing, debug,
creating and maintaining test environment/checkers/monitors, coverage, test
plans .Leadership qualities desired: leading group of 3-5 engineers,
mentoring, communicating with remote sites, driving functionality.Hands on
requirement a must.Education requirements: MS preferred, BS minimum. Goodinstutions a plus: IITs, RECs, BITs

For more information mail to: jabeena.m@alpconsulting.in

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Contract position 5-6 months: Front End Design / Verification, INFINEON Bangalore

Posted by verification job on August 17, 2010

Job Description : Consultant for Test Chip Front End Design and Verification Tasks

Skills: Technical Attributes

Mandatory:
* B.Tech/M.Tech in EE/EC from a reputed institution.
* Desirable : 1 year experience in VLSI Front End Flow, Freshers also can be considered, if they have some relevant project experience during studies.
* Knowledge of Verilog , VHDL and C is a must.
* Exposure to Verification Tools : Model Sim or Ncsim is a must, can consider FPGA expertise as well.
* Experience with Unix and Windows.
* A proactive team player with good written and verbal communication skills.
* Familiarity with one Configuration management System will be a plus.

Send relevant CVs to: Syed.Abrar@infineon.com
Note : We can also consider experienced professionals who are away from work for some time and would like to restart with a temporary position.

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Verification Engineer

Posted by verification job on August 12, 2010

Location: Noida
Must have 3-4 years experience in verification of complex digital ASICs/FPGAs. Must have created verification testbenches using SystemVerilog. Must have familiarity with Verilog or VHDL. Familiarity with OVM/UVM a plus. Domain knowledge of image processing, codecs or networking is desirable.

Please send in your resume to jobs@agnisys.com with a cover letter.
http://www.agnisys.com

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verification openings in a well established company, Bangalore(6 to 10yrs)

Posted by verification job on August 11, 2010

1) First Line Managers for Processor Verification or Circuit
Design/Layout
Brief Job Description: People manager for a group of 15-20
development engineers working on high end microprocessors. Position includes
all people managment tasks like managing organizational issues, ramping and
retaining a team, motivating employees, setting goals and providing feedback
for individual development. It further includes project management
tasks in a global development team, with focus on driving execution on cross
geographic projects out of Bangalore. Excellent communication skills, focus
on execution, and hands on and management background in processor
development in the areas of Verification or Circuit Design/Layout is required.

2) Implement verification plans to verify unit level, sub-system
and core / chip level functionality. Define, architect and build a robust and
re-usable verification environment for the core / chip.Solid understanding
of VHDL / Verilog based RTL designs. Verification coding experience in
System Verilog with OVM knowledge with good debugging expertize. Work closely
with design engineers to ensure adequate functional and code coverage, and
create fully random based testbench and testcases. Preference given to
candidates with formal verification experience. BTech, M Tech/MS with minimum 8+
years experience (atleast 3 yrs in a leadership role). 2 years
experience with System Verilog / Vera / Specman Constrained Random test-bench
knowledge.1 year experience with Assertion-Based Verification (SVA, PSL).
Excellent communication skills and ability to work with a global team

3) Brief Job Description: Experience in presilicon verification,
preferably processors or north bridges .Skills include test writing, debug,
creating and maintaining test environment/checkers/monitors, coverage, test
plans .Leadership qualities desired: leading group of 3-5 engineers,
mentoring, communicating with remote sites, driving functionality.Hands on
requirement a must.Education requirements: MS preferred, BS minimum. Good
instutions a plus: IITs, RECs, BITs

for more details mail to : jabeena.m@alpconsulting.in

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openings : Specman : Blr : 3 -7 yrs

Posted by verification job on August 7, 2010

Pls send me your updated resume for further processing.

Also let me know if you have any friends looking for job change with similar domain.

Skills:

HW Verification engineers with Knowledge of Specman
————————————————————–
. Architecting Verification environment using HVls like SPECMAN for IP Verification.
. Should have good knowledge of eRM Methodology . Development of Test plans . Development of Environment and Test cases . Good analytical skills required for RTL debug . Coverage, Regression and Verification closure . Good knowledge of eVC Architecture . Good knowledge of C / Verilog environment Development . Perl, Shell Scripting for automation . Domain knowledge of Storage Card technologies like SSD, Flash, UFS, UHS, SATA, USB

Desirable to have Experience on:

. Assertion based Verification( ABV), Coverage driven Verification (CDV), Functional coverage , Formal Verification(FV) , Full chip verification and debug . Good knowledge of Process and Documentation
Exp: 3 – 7 yrs

Email : raghupathy.v@adecco.co.in

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Openings for Entry level : Verilog Design : 0 – 1 Exp.

Posted by verification job on August 6, 2010

Location : Hyderabad
Exp : 0 to 1 exp
Requirement :

Digital Design
Micro controller
Verilog Design
FPGA

jobs@testbench.in

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