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Verification requirement in large semicon, bangalore

Posted by verification job on September 16, 2010

Position Requirements

Experience: 6+ years as a Verification Engineer or Design Engineer or Verification AE. Experience in leading verification teams to verify complex SOCs is a real plus.

Education BSEE min
Languages: System Verilog + Verilog, VHDL, Specman, Vera, C++, or SystemC

Methodologies: URM, MDV, UVM, AVM and/or VMM
Position Description

Extensive experience in creating Coverage Driven Verification environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ is required. Track record of successfully verifying complex ASICs is also required.
Track record of successfully verifying complex ASICs is also required.

Strong SystemC / C++ skills are a real plus.

For more information mail to:jabeena.m@alpconsulting.in

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VERIFICATION ENGINEER- URGENT

Posted by verification job on September 10, 2010

Exp: 2-3 yrs

Skills required: System Verilog,Verilog,Perl scripting,Linux fundamentals…

Protocol knowledge: DDR/MIPI/FCoE/USB 3.0/PCIe 3.0

Position @: Bangalore/ Bhubaneswar

Interested candidates kindly send their updated CV on nsaxena@perfectus.com and mihir.sah@gmail.com

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Juniper Networks hiring ASIC Engineers…

Posted by verification job on September 8, 2010

. Pls send you resume to shantonu@juniper.net

About Juniper ASIC
.

ASIC is the differentiator starting from our 1st router to our latest products. Our ASIC’s have been feature rich without sacrifice in performance.
Juniper ASIC Organizations mission is to deliver on-time, error-free, high performing, scalable, lowest cost, power efficient SILICON that is widely-deployable and beats the competition. We have developed 3 generations of high end router chipsets. ASIC was a differentiating factor for Juniper from our first product M40 to the latest T1600 and MX960. We have a track record of delivering 80+ ASIC’s , which were first time correct.
Currently we are working on the 45 nanometer technology (will be working on 32 nanometer going forward); 2.5- 3 million placeable objects; 30 million gates; 128 high speed links; clock frequency – 500- 800 MHz.

Juniper India Vision:
Our ASIC team in Bangalore is working on next generation router/switch chipset and owning multiple major blocks/modules. We are looking for talented individuals who will be part of excellent ASIC team. Design Engineers will go through the full cycle of ASIC development starting from Micro Architecture, RTL coding, Synthesis, Floor planning, Timing Closure to tape out. Verification engineers will develop architecture modelling, test benches, create tests, run code coverage, fullchip verification etc

ASIC Design Engineer
Job Summary
Responsible for block level/ full chip ASIC design
Responsibilities
 Develop micro-architecture and RTL implementation of large, complex high-speed ASIC’s for Juniper’s next generation of networking products.
 Develop detailed micro architectural specification, RTL code, synthesis, closure on pre-layout timing, involve in PD activities to ensure first working silicon.
 Develop module register specifications.
 Need to make and maintain block schedule and complete tasks on or before time.
 Work with verification engineers to close code coverage and ensure first-time working silicon.
 Work with global physical design and signal integrity teams to achieve timing closure in routed netlists.
 Mentor fresh graduate engineers with the design flow, strategy.
Qualification
 Strong Verilog, Synopsys DC/PT/ICC, C/C++, Perl/shell scripts or Vera programming skills.
 Must have good leadership/communication skills.
 Networking experience is highly desirable, but not required.
 Track record of successfully design of ASIC’s from start to finish.

ASIC Verification Engineer
Job Summary:
 Perform ASIC verification for large, complex high-speed ASIC’s for Juniper’s next generation of networking products.
 Responsible for block as well as fullchip/multichip verification
 Responsibilities
 Develop detailed test plans, block and system-level test benches and verification environments; execute and achieve complete coverage to ensure first working silicon.
 Develop functional models for architectural validation.
 Need to meet or exceed test-plan/chip schedule.
 You will work closely with logic designers to resolve bugs, software developers to assist in software and bring-up development.
 Mentor junior engineers with the verification flow, strategy.
 Develop Perl, Tcl and/or shell scripts to enhance current verification infrastructure/methodology.
Qualification
 Strong Verilog, SystemC or C/C++, Perl/shell scripts or Vera programming skills.
 Must have good leadership/communication skills.
 Networking experience is highly desirable, but not required.
 Track record of successfully delivered multiple ASIC’s from start to finish.

Pls feel free to mail me should you need any further clarification.

Thanks
Shantonu Ghosh
Juniper Networks | Recruiting Specialist
Email shantonu@juniper.net
LinkedIn http://www.linkedin.com/in/shantonu

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System C , 6+yrs

Posted by verification job on September 1, 2010

Looking for verification engineers System C , 6+yrs experience for large semicon bangalore For more information mail to: jabeena.m@alpconsulting.in

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DV Synapse Design

Posted by verification job on August 31, 2010

DV Synapse Design mike@synapse-da.com p

Bangalore

Design Verification

Create verification plans for SoC level verification

Create testbenches in C/C++

Utilize advanced verification techniques

Write tools and scripts in Perl and other script languages to enhance the verification process

Qualifications and requirements:

BS, MS, PhD, in computer science or engineering

Working knowledge of ARM-based processors and AMBA bus protocols

Experience with simulators from one or more of the major EDA suppliers (Cadence, Mentor or Synopsys)

Working knowledge of Verilog

Experience with tools for regression management, configuration management and bug tracking

Good problem solving and debugging skills

Qualifications: BS or MS

Experience: 4 to 12 yrs

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nSys – Verification Engineers

Posted by verification job on August 31, 2010

nSys hiring Verification Engineers Delhi Experience: 3 – 6 yrs Skills: Should be proficient in SystemVerilog OVM/VMM, AMBA/USB/PCIe/Ethernet/SAS/SATA protocol knowledge desirableInterested candidates, please send your CV to shilpa.verma@nsysinc.com

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Sr. Design Verification Engineer

Posted by verification job on August 30, 2010

Location: Xilinx India, Hyderabad

Contact: ravikir@xilinx.com
Detailed Description

Xilinx has a position for Senior Design Verification Engineer. The candidate for this position will architect and implement simulation verification environment, flows and infrastructure. Successful candidate will have proficiency in developing advanced verification flows.
The candidate will have an opportunity to help create reusable verification environments to be used across multiple projects.
The role involves VLSI functional verification including
• Developing coverage driven verification methodologies and flows
• Developing and implementing simulation and debug flows
• Developing functional coverage and coverage analysis environment
• Writing tools and scripts in Perl and other script languages to enhance the verification process
• Evaluating industry leading tools for use in design verification.
• Technical Leadership role including mentoring other engineers.

Job Requirements

BS/MS in EE, Computer Engineering, or equivalent field.
Strong Software programming background
Strong verification background and proven experience in architecting and implementing verification tools and flows. Strong programming skills in Verilog and hardware verification languages (HVLs) such as SystemVerilog, Vera or Specman ‘e’.
Programming skill and experience in one or more of C, C++ and perl is a strong plus. Comfort with a diversity of programming environments and tools. Experience with a reuse methodology/class library, such as VMM, OVM, RVM. Experience with Oriented Programming (OOP) techniques
Experience with developing verification tools like random code generators, regression management tools and automation of verification is highly desirable

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Staff Design Verification Engineer (Manager / Sr Manager – Central Verification Methodology Team)

Posted by verification job on August 30, 2010

Location: Xilinx India, Hyderabad;

Contact: ravikir@xilinx.com
Detailed Description:
Xilinx has a position for Staff Design Verification Engineer. The candidate for this position will architect and implement Test Benches, including random environment, error generation, checkers and monitors. Successful candidate will have proficiency in efficiently developing advanced verification environments. The candidate will have an opportunity to help create reusable verification environments to be used across multiple projects.
The role involves VLSI functional verification including
• Developing coverage driven verification envirnoments
• Developing and implementing verification plans
• Creating assertions with SystemVerilog (SVA) and verifying using static tools or simulator
• Developing functional coverage and coverage analysis
• Developing simulation infrastructure and debug environments.
• Writing tools and scripts in Perl and other script languages to enhance the verification process
• Evaluating industry leading tools for use in design verification.
• Technical Leadership role including mentoring other engineers.

Job Requirements:
• 12+ yrs of Relevant experience with BS/MS in EE, Computer Engineering, or equivalent field.
• Strong verification background and proven experience in architecting and implementing comprehensive test benches. Strong programming skills in Verilog/VHDL and hardware verification languages (HVLs) such as SystemVerilog, Vera or Specman ‘e’.
• Programming skill and experience in one or more of C, C++ and perl is a strong plus. Comfort with a diversity of programming environments and tools. Experience with a reuse methodology/class library, such as VMM, OVM, RVM. Experience with Oriented Programming (OOP) techniques
• Experience with developing verification tools like random code generators, regression management tools and automation of verification is highly desired.
• Experience with emulation system and formal verification a plus

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Design Verification Engineer

Posted by verification job on August 30, 2010

Location: Xilinx India, Hyderabad

Contact: ravikir@xilinx.com
Job Description:
Xilinx is currently looking for a dynamic individual to work within the Processor Solutions and Global Verification Group on the next-generation SOC ASIC design. The individual will manage and contribute to the architecture and implementation of the verification testbench using System Verilog and OVM. This individual will work closely with designers to develop a testplan and a stand-alone methodology that is easily portable and reusable within the system testbench. The individual needs to work with teams who are in different geographical areas.
Responsibilities include definition of the verification methodology and the testbench architecture, review of the verification specs, cover groups, and test plans, development of constraint-random stimulus generators, bus-functional models, scoreboards, etc.
Job Requirements

• BS/MS EE, CE, or CS
• 4+ years of design verification experience
• 2+ years of OOP coding experience (VERA, System Verilog, SpecmanE or C++) and SV Assertions
• Strong Familiarity with Verification Methodologies such as OVM, AVM, or VMM
• Familiarity with Verilog and General Logic Design concepts
• Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR2/DDR3, and peripherals such as USB and Ethernet
• Strong working knowledge of UNIX environment and scripting languages such as Perl or Python
• Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim
• Experience using UNIX Revision Control tools – Subversion, RCS, CVS, Perforce and bug tracking tools such as Bugzilla
• Experience in verifying multimillion gate chip designs from specifications to tape-out
• Excellent communication and presentation skills
• Excellent leadership and project management skills
• Demonstrate the ability to work with cross-functional teams
• Familiarity with processors and SOC Debug architectures such as Coresight is a plus
• Familiarity Software development flow including assembly and C is beneficial

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nSys hiring Verification Engineers (Delhi)

Posted by verification job on August 27, 2010

Position: Sr Verification Engineer
Job Location: Delhi
Experience: 3 – 6 yrs
Skills: Should be proficient in SystemVerilog (OVM/VMM), AMBA/USB/PCIe/Ethernet protocol knowledge desirable

Interested candidates, please send your CV to jp@nsysinc.com

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