Verification job's Blog

Brought to you by www.testbench.in

Archive for June, 2010

Very Challenging Position with an leading EDA company in Noida for their VIP group!!

Posted by verification job on June 29, 2010

Dear Associates,

Good day!!

Amim here from Cyborg Technologies . We are an International Executive Search firm , working with top most product companies in IT , Semiconductor , EDA domain.

Came across a really very challenging position with an EDA industry for their VIP group.

The company is a leader in electronic design automation. We enable companies to develop better electronic products faster and more cost-effectively.

Our innovative products and solutions help engineers conquer design challenges in the increasingly conquer design challenges in the increasingly complex worlds of board and chip design.

Position Title: MTS-Verification IP Team (Noida)

Responsibilities:

Extensive experience in

Industry std. interfaces like USB, PCI Express, Ethernet, PCI, HDMI, SATA

Develop Verification IP using different languages and methodologies

System Verilog VIP using VMM or AVM

Vera VIP using RVM

eVC using eRM

Assertion IP development using SVA, PSL or OVA.

Design IP validation using different VIPs

IP development for standard or proprietary interface

Be an integral part of a team that is developing checkers and protocol monitors, such as PCI Express and 10 Gigabit Ethernet, for use with 0-In’s advanced functional verification tools and Questa RTL simulation. 0-In’s checkers and monitors help design teams find more bugs in less time than conventional simulation techniques.

You will specify, implement, test, and manage regression tests for standard checkers and protocol monitors for a wide range of end user applications, as well as custom checkers and monitors for specific customers. You will interact with TMEs and CSDs or directly with customers to resolve customer issues.

Academic Qualification: BE/ME/Mtech

Experience: 1to 4 years of relevant experience

Would really appreciate if you could share some references.

Looking forward to hear from you.

Pls share your work profile at amim@cyborg.co.in

PS: We are having 10 open positions:)

Posted in Uncategorized | Leave a Comment »

Verification Manager

Posted by verification job on June 29, 2010

12-15+ Yrs experience He or she from good technical skills as well people management skill He or she has to manage the entire verification team across the globe He or she should have great enthusiasm, who can start the things from scratch. If you are intersted contact me on below mentioned contact details. Thanks, Bibin S bibin.sundaran@careernet.co.in 9611833167

Posted in Uncategorized | Leave a Comment »

LEAD RECRUITER – ASIC Practice (Bangalore)

Posted by verification job on June 28, 2010

Looking at 2 very strong resources in the Semiconductor / EDA search domain. You should possess over 12 months of experience to take on resourcing as well as client handling. Exceptional communication and relationship skills.

About us : We are a 6 month young start up company but with an exceptional client list and still growing. We are currently 5 people and looking to grow to over 20 people in the next 3 months purely on the Products space.

Call me : +91-9902827800

Mail me : vinay@onssearch.in

COMPENSATION is best in class.

Posted in Uncategorized | Leave a Comment »

Principal Design Engineer requirement in large semicon, Bangalore.

Posted by verification job on June 28, 2010

Requirement 1

Required Skills: 8 – 12 years of experience

Expertise in RTL Coding using Verilog and System Verilog Languages

Knowledgeable in Chip level Design and Integration activities

Hands on Experience with C and Assembly Programming Languages

Proficiency in common UNIX scripting languages (Perl, csh, sh.)

Excellent debug skills in both functional and gate level simulations

Good Knowledge of SOC peripherals like ADC/Timers/ECAN/USB/Ethernet

Knowledge of revision control tools such as CVS

Superior Written and Verbal Communication skills

Extensive experience working with global teams and independently handles expectations

Desired Skills:

Experience with MIPS CPU subsystem

Experience with Verification Methodologies such as Vera or VMM

Knowledge of Programming Languages such as C++ or System C

Experience with synthesis and static timing tools

Knowledge and exposure to complete SOC tape-out flow is desired

Requirement 2

Required Skills: 8 – 12 years of experience

Expertise in RTL Coding using Verilog/System Verilog Languages.

Knowledgeable in Chip level Design/Integration activities.

Hands on Experience with C & Assembly Programming Languages.

Proficiency in common UNIX scripting languages (perl, csh, sh.).

Excellent debug skills in both functional and gate level simulations

Good Knowledge of SOC peripherals like ADC/Timers/ECAN/USB/Ethernet

Superior Written and Verbal Communication skills.

Extensive experience working with global teams and independently handles expectations.

Desired Skills:

Exposure to CPU subsystem Design/Simulation is a plus

Experience with VMM Methodology is a plus.

Knowledge/exposure to complete SOC tape-out flow is desired

For more information mail to: jabeena@mindsoftconsulting.com

Posted in Uncategorized | Leave a Comment »

Digital Front End verification requirement in large semicon, Bangalore.

Posted by verification job on June 28, 2010

Requirements: 1. 5 to 6 yrs Experience in the field of Digital Front End verification 2. Sound knowledge of industry standard protocols [SPI, I2C, USB, ETHERNET…] 3. Sound knowledge of Module and System-level verification using assembly based/HVL 4. Hands on experience in writing testcases, developing verification requirements, verification plan at module/system level 5. Exposure to Microcontroller/Microprocessor architecture 6. Exposure to System-Verilog is an advantage 7. Capable of either working independently OR leading 1-2 junior engineers/Interns For more information mail to: jabeena@mindsoftconsulting.com

Posted in Uncategorized | Leave a Comment »

Verification Engineers & Senior Verification Engineers required immediately

Posted by verification job on June 24, 2010

If you have the Confidence & potential to grow with the best design service provider in VLSI industry, then rush your resumes to mithungn@whizchip.com

We are looking for,

Experience : 3 to 6 Years
HVLs : Verilog, System Verilog or Specman or C++
Scripting Languages : Perl, Tcl, Makefiles
Methodologies : VMM, OVM, eRM or UVM
Preferred Protocol knowledge : PCIe, USB, etc
Experience in : Microcontroller / Microprocessor Based, MIPS based SoCs,

Posted in Uncategorized | Leave a Comment »

Sr DV engineer with 3-5 years of experience with Specman

Posted by verification job on June 24, 2010

Sr DV engineer with 3-5 years of experience with SpecmanHighlights are: – Hands on experience with FPGA design verification and simulation languages and tools including Vera, Specman, System Verilog – Experience with lab bring up, debugging and design validation of FPGA – Proficiency with hardware test and measurement equipment including oscilloscope and logic analyzer – RTL design Verilog/VHDL expertise – Board design expertise is a plus Note: Requires 3-5 years experience with Specman External Job Description r: The job involves working as part of a team verifying high end network FPGAs, the candidate will be involved with all aspects of FPGA verification including but not limited to: – infrastructure development – authoring of test plans – test plan execution – coverage and code reviews position is located in Silicon Valley, California Please email us at careers@sedaa.net

Posted in Uncategorized | Leave a Comment »

Senior Verification Engineer with Specman experience.

Posted by verification job on June 22, 2010

looking for one experienced Senior Verification Engineer with Specman experience. Job is 3-6 months. Position is available for US Permanent Resident or Citizen only.

Mark Chen ( markc@tripleco.com )

Posted in Uncategorized | Leave a Comment »

ASIC – Design Verification [ ASIC, Verification,RTL design, Synthesis ] 7-10yrs : Pune

Posted by verification job on June 19, 2010

Urgent Requirement : ASIC – Design Verification [ ASIC, Verification,RTL design, Synthesis ] 7-10yrs : Pune [India]Requirements: BS in EE/CS MS preferred or equivalent plus 7 to 10 years work experience. In-depth understanding of Computer architecture, RISC processors and EDA flows and tools. Understanding of system level designs, multi-processor communications and bus bridge design Experience/ familiarity in front end Verilog/VHDL design synthesis Understanding of embedded systems, software flows and experience with software tools, IDE will be a big plus Willingness to resolve Customer problems in both software and hardware domains. Must have excellent written and verbal communication skills as well as good problem solving skills. If interested kindly forward your updated resume to the email address hr@impetuspeople.com

Posted in Uncategorized | Leave a Comment »

Senior Verification Engineer (VMM)in San Diego,

Posted by verification job on June 17, 2010

** Senior Verification Engineer (VMM) **
~

We have an immediate need for a full-time Senior Verification Engineer (VMM) to join our team in San Diego, California.

Detailed skills and tools required:

• Career verification resource with full chip level experience.
• Expertise (multi-year) in VMM methodology.
• Ability to set up SystemVerilog/VMM verification environment, top level test benches, simulations, test code coverage, debug.
• Create and execute complex verification plans.
• Technical expert in creating/enhancing tools/scripts and overall verification environment.
• Strongly desired: Domain knowledge/expertise in Bluetooth, 802.11, WLAN, MAC and PHY verification.

ABOUT US

Rapid Bridge has created a unique and patented way of designing and integrating Semiconductor Intellectual Property (IP) that reduces duplicated resources out of chips that result in die size reductions of up to 20%. With the die size reduction benefit we have also added a configurability component that reduces TTM (Time to Market), NRE and Tooling costs. Along with our revolutionary approach to IP integration we have a methodology that lowers digital logic power and area while also improving performance all concurrently. Improving all there (Power, Performance and Area) chip metrics simultaneously is an industry first and provides Rapid Bridge a tremendous differentiation value. CPR technology: Improve Power, Performance and Area (PPA) of core logic area by > 50%, up to now, the factor of PPA has held at 1 for years. Our products include Semiconductor IP, full turn key ASIC services and comprehensive design services. On March 22, 2010, Rapid Bridge acquired QuantumThink Group, Inc. (QThink), a San Diego-based, privately-held IC design services company with offices in San Jose, California and Bangalore, India. The acquisition will enable Rapid Bridge to offer its clients full front-to-back IC design services (full article http://rapidbridge.com/220310.php ).

Rapid Bridge is located in the San Diego Tech Center which features an abundance of amenities that makes this campus an ideal and productive location for tenant employees – http://www.mpgoffice.com/SanDiegoTechCenter/index.php – click on the San Diego Tech Center Building Fact Sheet and E-brochure to see all the cool amenities we have!

Interested and qualified candidates please send your resume to jleon@rapidbridge.com

Posted in Uncategorized | Leave a Comment »