Specman Verification with 5 to 10 Yrs

we are looking for Specman Verification with 5 to 10 Yrs experience in large semiconductor company -Hyderabad
Required Skills:

Should have worked with ARM based designs which include DDR controllers (DDR1/2/3)

Minimum 2+ years of working experience with AXI, AHB and APB

Minimum 4+ years of verification experience with C/PLI based verification environments and/or High level verification languages like Specman using NCSIM simulator

Minimum 3+ years of RTL verification experience with Specman/HVL. Domain knowledge on design/verification of dynamic memory controllers (SDR, DDR, DDR2 and future technologies) is a MUST.

Must have ASIC design experience developing and verifying memory controller ASIC’s for SDRAM, DDR, QDR, burst/page and async NOR and NANDFLASH. The critical areas are SDRAM & DDR, plus extensive experience with interface characterization.

Responsibilities also include verification of ASIC at full chip level, develop detailed test plan and regression suites and be responsible for their implementation, run gate level timing simulations and work with design engineers to achieve complete coverage to get first working silicon.

Experienced in C/C++ with a thorough knowledge on object oriented programming will be a plus. Experience in writing BFMs, cycle/transaction-accurate modeling is a must.

Working experience with high speed serial interfaces like USB 2.0, SATA, PCI-express will be a plus.

Should be skilled at isolating and identifying design bugs

Broad understanding of RTL-to-Tapeout methodology

Working knowledge of csh/perl scripting

Must be a good team player

Nice to have:

Experience with other on-chip buses like OCP is a plus

Experience with Verilog/PSL/OVA assertions is a plus

Experience with developing BFMs for stimulus generation, checking and bus monitors is a plus

Prior experience in working with remote teams is a plus

Location: Hyderabad

If interested Pls share your updated profile to purvi@mindsoftconsulting.com

Verification

Verification Manager,Sr Verification Engineers(10+yrs) in large semicon, Blr
1. Verification Manager Req

Job Requirement:

· MSEE with 10+ years or BS with 12+ years in chip design and verification.

· Experience in managing 2 to 5 engineers.

· Worked in the US or a US based company in India for 5+ years.

· Should have worked as an individual contributor in an ASIC verification background for 5 years.

· Experience in verification lead position.

· Experience in planning the verification process, resource allocation and creating realistic schedule estimates.

· Experience in developing coverage-driven verification test plans.

· Experience writing test specifications (plans) and creating directed and random test cases.

· Experience managing regression analysis

· Experience in high level Object Oriented test bench environments such as VMM/UVM .

· Strong System Verilog, PERL, TCL, and C/C++ programming skills

· Experience in planning the verification process and coming up with realistic schedule estimates.

· Able to adopt the use of new techniques and methodologies and promote their use within the project.

· A high level of pro-activity, initiative and problem solving.

· Familiarity with constrained random and assertion based verification is preferred

· Verification experience in SERDES, Ethernet Networking in Verilog is a big plus.

· Knowledge of SONET and IEEE 802.3 Physical layer clauses is a plus.

2. Sr Verification Engineers Req

Job Requirement:

· MSEE with 10+ years or BS with 12+ years in chip design and verification.

· Worked in the US or a US based company in India for 5+ years.

· Should have worked as an individual contributor in an ASIC verification background for 5 years.

· Experience in verification lead position.

· Experience in planning the verification process and creating realistic schedule estimates.

· Experience in developing coverage-driven verification test plans

· Experience writing test specifications (plans) and creating directed and random test cases.

· Experience managing regression analysis

· Experience in high level Object Oriented test bench environments such as VMM/UVM .

· Strong System Verilog, PERL, TCL, and C/C++ programming skills

· Experience in planning the verification process and coming up with realistic schedule estimates.

· Able to adopt the use of new techniques and methodologies and promote their use within the project.

· A high level of pro-activity, initiative and problem solving.

· Familiarity with constrained random and assertion based verification is preferred

· Verification experience in SERDES, Ethernet Networking in Verilog is a big plus.

· Knowledge of SONET and IEEE 802.3 Physical layer clauses is a plus.

For more information: jabeena.m@alpconsulting.in
Mobile: 9538716955

Verification IP Engineer (for Mentor Graphics Noida)

pls send your profiles to anuj_agarwal@mentor.com
JD FOR VIP

Job Responsibilities:
Be an integral part of a team that is developing checkers and protocol monitors, such as PCI Express and 10 Gigabit Ethernet, for use with 0-In’s advanced functional verification tools and Questa RTL simulation.
0-In’s checkers and monitors help design teams find more bugs in less time
than conventional simulation techniques.
You will specify, implement, test, and manage regression tests for standard checkers and protocol monitors for a wide range of end user applications, as well as custom checkers and monitors for specific customers. You will interact with TMEs and CSDs or directly with customers to resolve customer issues.

Job Requirements:
• Solid Verilog HDL RTL knowledge
• Solid RTL simulation and test bench experience
• Intimate knowledge of one or more standard bus protocols
• Solid engineering
• B.Tech/M.Tech in electrical engineering or related field
• 1-3 years of experience in verification engineering

Desired Requirements:
• Experience with cycle-based simulation and constrained-random simulation
• Knowledge of assertion languages or libraries, such as PSL, SVA, OVL
• VHDL & System Verilog HDL RTL knowledge
• Experience with System C or C++
• Experience with Specman Elite or Vera/NTB
• Experience with Formal Property Verification tools

Other Requirements:
Bus Protocol know how with SV, AVM, Vera, Specman knowhow etc.

Verification requirement in large semicon, bangalore

Position Requirements

Experience: 6+ years as a Verification Engineer or Design Engineer or Verification AE. Experience in leading verification teams to verify complex SOCs is a real plus.

Education BSEE min
Languages: System Verilog + Verilog, VHDL, Specman, Vera, C++, or SystemC

Methodologies: URM, MDV, UVM, AVM and/or VMM
Position Description

Extensive experience in creating Coverage Driven Verification environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ is required. Track record of successfully verifying complex ASICs is also required.
Track record of successfully verifying complex ASICs is also required.

Strong SystemC / C++ skills are a real plus.

For more information mail to:jabeena.m@alpconsulting.in

VERIFICATION ENGINEER- URGENT

Exp: 2-3 yrs

Skills required: System Verilog,Verilog,Perl scripting,Linux fundamentals…

Protocol knowledge: DDR/MIPI/FCoE/USB 3.0/PCIe 3.0

Position @: Bangalore/ Bhubaneswar

Interested candidates kindly send their updated CV on nsaxena@perfectus.com and mihir.sah@gmail.com

Juniper Networks hiring ASIC Engineers…

. Pls send you resume to shantonu@juniper.net

About Juniper ASIC
.

ASIC is the differentiator starting from our 1st router to our latest products. Our ASIC’s have been feature rich without sacrifice in performance.
Juniper ASIC Organizations mission is to deliver on-time, error-free, high performing, scalable, lowest cost, power efficient SILICON that is widely-deployable and beats the competition. We have developed 3 generations of high end router chipsets. ASIC was a differentiating factor for Juniper from our first product M40 to the latest T1600 and MX960. We have a track record of delivering 80+ ASIC’s , which were first time correct.
Currently we are working on the 45 nanometer technology (will be working on 32 nanometer going forward); 2.5- 3 million placeable objects; 30 million gates; 128 high speed links; clock frequency – 500- 800 MHz.

Juniper India Vision:
Our ASIC team in Bangalore is working on next generation router/switch chipset and owning multiple major blocks/modules. We are looking for talented individuals who will be part of excellent ASIC team. Design Engineers will go through the full cycle of ASIC development starting from Micro Architecture, RTL coding, Synthesis, Floor planning, Timing Closure to tape out. Verification engineers will develop architecture modelling, test benches, create tests, run code coverage, fullchip verification etc

ASIC Design Engineer
Job Summary
Responsible for block level/ full chip ASIC design
Responsibilities
 Develop micro-architecture and RTL implementation of large, complex high-speed ASIC’s for Juniper’s next generation of networking products.
 Develop detailed micro architectural specification, RTL code, synthesis, closure on pre-layout timing, involve in PD activities to ensure first working silicon.
 Develop module register specifications.
 Need to make and maintain block schedule and complete tasks on or before time.
 Work with verification engineers to close code coverage and ensure first-time working silicon.
 Work with global physical design and signal integrity teams to achieve timing closure in routed netlists.
 Mentor fresh graduate engineers with the design flow, strategy.
Qualification
 Strong Verilog, Synopsys DC/PT/ICC, C/C++, Perl/shell scripts or Vera programming skills.
 Must have good leadership/communication skills.
 Networking experience is highly desirable, but not required.
 Track record of successfully design of ASIC’s from start to finish.

ASIC Verification Engineer
Job Summary:
 Perform ASIC verification for large, complex high-speed ASIC’s for Juniper’s next generation of networking products.
 Responsible for block as well as fullchip/multichip verification
 Responsibilities
 Develop detailed test plans, block and system-level test benches and verification environments; execute and achieve complete coverage to ensure first working silicon.
 Develop functional models for architectural validation.
 Need to meet or exceed test-plan/chip schedule.
 You will work closely with logic designers to resolve bugs, software developers to assist in software and bring-up development.
 Mentor junior engineers with the verification flow, strategy.
 Develop Perl, Tcl and/or shell scripts to enhance current verification infrastructure/methodology.
Qualification
 Strong Verilog, SystemC or C/C++, Perl/shell scripts or Vera programming skills.
 Must have good leadership/communication skills.
 Networking experience is highly desirable, but not required.
 Track record of successfully delivered multiple ASIC’s from start to finish.

Pls feel free to mail me should you need any further clarification.

Thanks
Shantonu Ghosh
Juniper Networks | Recruiting Specialist
Email shantonu@juniper.net
LinkedIn http://www.linkedin.com/in/shantonu

System C , 6+yrs

Looking for verification engineers System C , 6+yrs experience for large semicon bangalore For more information mail to: jabeena.m@alpconsulting.in