Verification(system verilog/specman) requirement openings in large semicon, bangalore (8+yrs)

Requirement 1

Implement verification plans to verify unit level, sub-system and core / chip level functionality. Define, architect and build a robust and
re-usable verification environment for the core / chip.Solid understanding
of VHDL / Verilog based RTL designs. Verification coding experience in
System Verilog with OVM knowledge with good debugging expertize. Work closely with design engineers to ensure adequate functional and code coverage, and create fully random based testbench and testcases. Preference given to candidates with formal verification experience. BTech, M Tech/MS with minimum 8+years experience (atleast 3 yrs in a leadership role). 2 years
experience with System Verilog / Vera / Specman Constrained Random test-bench knowledge.1 year experience with Assertion-Based Verification (SVA, PSL).
Excellent communication skills and ability to work with a global team

Requirement 2

Brief Job Description: Experience in presilicon verification,
preferably processors or north bridges .Skills include test writing, debug,
creating and maintaining test environment/checkers/monitors, coverage, test
plans .Leadership qualities desired: leading group of 3-5 engineers,
mentoring, communicating with remote sites, driving functionality.Hands on
requirement a must.Education requirements: MS preferred, BS minimum. Goodinstutions a plus: IITs, RECs, BITs

For more information mail to: jabeena.m@alpconsulting.in