Verification IP Engineer (for Mentor Graphics Noida)

pls send your profiles to anuj_agarwal@mentor.com
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Job Responsibilities:
Be an integral part of a team that is developing checkers and protocol monitors, such as PCI Express and 10 Gigabit Ethernet, for use with 0-In’s advanced functional verification tools and Questa RTL simulation.
0-In’s checkers and monitors help design teams find more bugs in less time
than conventional simulation techniques.
You will specify, implement, test, and manage regression tests for standard checkers and protocol monitors for a wide range of end user applications, as well as custom checkers and monitors for specific customers. You will interact with TMEs and CSDs or directly with customers to resolve customer issues.

Job Requirements:
• Solid Verilog HDL RTL knowledge
• Solid RTL simulation and test bench experience
• Intimate knowledge of one or more standard bus protocols
• Solid engineering
• B.Tech/M.Tech in electrical engineering or related field
• 1-3 years of experience in verification engineering

Desired Requirements:
• Experience with cycle-based simulation and constrained-random simulation
• Knowledge of assertion languages or libraries, such as PSL, SVA, OVL
• VHDL & System Verilog HDL RTL knowledge
• Experience with System C or C++
• Experience with Specman Elite or Vera/NTB
• Experience with Formal Property Verification tools

Other Requirements:
Bus Protocol know how with SV, AVM, Vera, Specman knowhow etc.