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Archive for May, 2010

Looking for Front end design,synthesis engineers(2 to 7yrs) with experience

Posted by verification job on May 30, 2010

Looking for Front end design,synthesis engineers(2 to 7yrs) with experience in equivalence checker/ formality / LEC/ Conformal
Position Requirements
•Knowledge of the FrontEndDesign/VIP Design Flow
•2 to 6 years of Experience with FrontEnd Design/VIP tools from Cadence, Mentor
•Excellent knowledge of computers (including software installation)
•Excellent communication and interpersonal skills
•Fluent in English (written and verbal)

Position Description
The Support Applications Engineer (AE) will provide direct technical customer support for company’s products and will focus on applying technical expertise in multiple products within a specific technology family. The person should be able to act as strong team member and contributor, participate in team projects and initiatives. Expertise in RTL Compiler, Conformal, Encounter Test or VerificationIP, are added advantage.
The person should possess team-success orientation, mature work attitude, and good judgment under pressure.

For more details mail to:jabeena@mindsoftconsulting.com
Mobile: 9538716955

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Digital Sr IC Engineer in Porto Alegre Brazil

Posted by verification job on May 30, 2010

Job Description – Responsibilities

Responsible responsible for the design of mixed-signal integrated circuits for RFID and wireless applications.
This position will report to Digital Group Manager.

Requirements
– Bachelor’s degree in Electrical Engineering or computer science
– 7+ years experience in commercial IC design
– 5+ years experience in digital IC design
– excellent technical skills
– good knowledge of RTL coding using Verilog
– Experience in using IC design environment such as Synopsys or Cadence
– fluent in English

Additional Skills
– Previous experience in RFID products
– DFT knowledge
– Portuguese
Relocation Package includes move-in, tickets for employee and family.
Salário ca. 80k U$/year
Location: Porto Alegre RS
Please CV for: edelweis@ceitec-sa.com

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Excellent opportunity for a verification engineer. Position in Cesarea, Israel.

Posted by verification job on May 30, 2010

Requirements:
– Electrical Eng. Or Computer Science
– Specman (best) or SystemVerilog a must
– 2-4 years in verification, including environment writing and actually verifying a DUT to tape out.
Please, email your CV to ariela.dreyfuss@and-hc.co.il

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verification engineers – (Specman/System verilog based ASIC verification)

Posted by verification job on May 30, 2010

Large MNC Bangalore is looking for High end verification engineers – (Specman/System verilog based ASIC verification) for their over seas projects
If interested send your profile to jabeena@mindsoftconsulting.com/Mobile: 9538716955

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mixed signal Verification LEADs

Posted by verification job on May 29, 2010

Leading Semicon MNC in Bangalore needs mixed signal Verification LEADs with exp in PHY/PHY Layer/IP/Analog. Interested candidates – Pls send CV to ruchi@cmctechjobs.com/ 09811026286
Strong exp in Mixed signal Verification
PHY/PHY Layer/IP/Analog Verification exp must

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Application Engineering Consultant -Mentor Graphics Corporation

Posted by verification job on May 28, 2010

Mentor Graphics Corporation

Job Posting Title
Application Engineering Consultant / 50255740

Reference Code
50255740E

City
Bangalore

Job Requirements
• Assisting global customers deploy Mentor Graphics’ HDL-based design and Scalable Verification software to solve ASIC/FPGA design challenges.
• Supporting HDL-based design and functional verification software in pre-sales and post-sales situations, both on-site in global customers’ locations and from your office.
• Helping Global Account Managers determine sales execution strategy by identifying and qualifying the match-up between global customer needs and Mentor Graphics’ HDL-based design and Scalable Verification software products.
• Illustrating the value Mentor Graphics brings to global customers by:
o Troubleshooting technical obstacles to the deployment of Mentor Graphics’ HDL-based design and Scalable Verification software
o Developing and delivering software demonstrations and technical presentations;
• Communicating global customers’ technical requirements to product marketing;
• Assisting global customers with their software evaluations and benchmarks.
• Developing a network of technical relationships at a peer-to-peer level with global customers.
• Managing and coordinating the technical relationships between global customers, the Mentor Graphics’ Global Account team and product marketing.

Job Qualifications
• BE/BTech. with minimum 4 years on functional verification. At least one of the following:
1. Hands-on functional verification experience on large ASIC (2M+ gates).
2. Experience in a support/sales role on any functional verification tools technologies.
• Ideal candidates will also have two or more years of sales experience working in a high paced team sales environment, with strong communications and interpersonal skills
• Must have a conceptual understanding of VLSI Device verification.
• Should be willing to train the customer on-site.
• Excellent communication skills and people skills.
• Experience on PERL and shell scripts desired
• Experience with HDL-based, register-transfer-level (RTL), digital logic design, verification languages, and functional verification methodology, for ASICs and/or FPGAs. This experience should include some of the following: VHDL and Verilog HDL simulation, synthesis and static timing analysis plus Assertion-Based Verification, including familiarity with OVL assertions, SystemC, SystemVerilog and/or PSL.

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Mentor Graphics Corporation – Lead Member Technical Staff

Posted by verification job on May 28, 2010

Job Posting Title
Lead Member Technical Staff / 50255757

Reference Code
50255757E

City
Noida

Job Requirements
This will be a product specialist – Tier 2 support job. The candidate should have experience in verification and design.Good knowledge in HDLs and scripting. Person should have worked in the Verification domain with good knowledge of System Verilog, SystemC/C/C++ and VHDL Strong SystemVerilog is highly desirable. Knowledge of OVM and VMM is added advantage.

Job Qualifications
B.E./ B. Tech / M. Tech. in Computer Science / Electrical / Electronics Engineering from reputed Universities / IITs / RECs with 3-6 years of experience.

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Mentor Graphics Corporation Senior Member Technical Staff

Posted by verification job on May 28, 2010

Mentor Graphics Corporation

Job Posting Title
Senior Member Technical Staff / 50255749

Reference Code
50255749E

City
Noida

Job Requirements
Development of C++/HDL models. The work will involve model design, implementation & validation. Skills : Hands on experience with C/C++ language, data structure,Verilog and SystemVerilog & simulation and prior experience on hardware protocols.

Job Qualifications
B.E./ B. Tech / M. Tech. In Computer Science / Electrical Electronics Engineering from reputed Universities / IITs / RECs

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Design Verification Engineer – LSI – Bangalore

Posted by verification job on May 28, 2010

Requisition Number : 10-6022
Job Title : Design VerificationEngineer 1
Country : India (IN)
State/Province/County : Karnataka
City : Bangalore
Requirements/Qualifications (Education) : • Masters in Engineering/ Bachelors in Engineering from a reputed institute (IIT/NIT) with good academic record (min 70%)
Job Description : Experience:
• Minimum 0-3 Years of verification experience in setting up the Test Bench, Environment and test cases development and execution
• Experience in verification of digital signal processor cores
• Experience in validation of design using Emulation like Palladium
• Candidate must have relevant experience from a good company

Job profile:
• Should setup the Palladium based validation flow. Make choices and decisions to port the System Verilog based test bench to Palladium platform
• Participate in the architecture and design of Verification environments, debate and suggest right verification methodologies for a given design/project.
• Should lead a team of engineers
• Generate Palladium based verification and test plans
• Should be able to debug the RTL and interact with the designers for the failures seen in emulation or verification

Required knowledge and skills:
• VLSI Design flows
• Expertise in HDLs (Verilog/VHDL)
• Emulation experience using Palladium
• Verification methodologies
• Expertise in System Verilog based verification and Industry standard verification methodologies
• Good communication skills
• Logic and Circuit design

Desirable Skills
• Familiarity with Scripting languages and a high level programming language
• RTL Design using Verilog or VHDL

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Sr.Specman/”e” Verification Engineers with 2-6yrs experience

Posted by verification job on May 28, 2010

Looking for Sr.Specman/”e” Verification Engineers with 2-6yrs experience in VLSI Industry.

The work location would be Bangalore.

Pls update your profiles to ravi.h.kumar@kpitcummins.com

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