Verification requirement in large semicon, bangalore
Posted by verification job on September 16, 2010
Experience: 6+ years as a Verification Engineer or Design Engineer or Verification AE. Experience in leading verification teams to verify complex SOCs is a real plus.
Education BSEE min
Languages: System Verilog + Verilog, VHDL, Specman, Vera, C++, or SystemC
Methodologies: URM, MDV, UVM, AVM and/or VMM
Extensive experience in creating Coverage Driven Verification environments utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ is required. Track record of successfully verifying complex ASICs is also required.
Track record of successfully verifying complex ASICs is also required.
Strong SystemC / C++ skills are a real plus.
For more information mail to:firstname.lastname@example.org