Juniper Networks hiring ASIC Engineers…

. Pls send you resume to shantonu@juniper.net

About Juniper ASIC
.

ASIC is the differentiator starting from our 1st router to our latest products. Our ASIC’s have been feature rich without sacrifice in performance.
Juniper ASIC Organizations mission is to deliver on-time, error-free, high performing, scalable, lowest cost, power efficient SILICON that is widely-deployable and beats the competition. We have developed 3 generations of high end router chipsets. ASIC was a differentiating factor for Juniper from our first product M40 to the latest T1600 and MX960. We have a track record of delivering 80+ ASIC’s , which were first time correct.
Currently we are working on the 45 nanometer technology (will be working on 32 nanometer going forward); 2.5- 3 million placeable objects; 30 million gates; 128 high speed links; clock frequency – 500- 800 MHz.

Juniper India Vision:
Our ASIC team in Bangalore is working on next generation router/switch chipset and owning multiple major blocks/modules. We are looking for talented individuals who will be part of excellent ASIC team. Design Engineers will go through the full cycle of ASIC development starting from Micro Architecture, RTL coding, Synthesis, Floor planning, Timing Closure to tape out. Verification engineers will develop architecture modelling, test benches, create tests, run code coverage, fullchip verification etc

ASIC Design Engineer
Job Summary
Responsible for block level/ full chip ASIC design
Responsibilities
 Develop micro-architecture and RTL implementation of large, complex high-speed ASIC’s for Juniper’s next generation of networking products.
 Develop detailed micro architectural specification, RTL code, synthesis, closure on pre-layout timing, involve in PD activities to ensure first working silicon.
 Develop module register specifications.
 Need to make and maintain block schedule and complete tasks on or before time.
 Work with verification engineers to close code coverage and ensure first-time working silicon.
 Work with global physical design and signal integrity teams to achieve timing closure in routed netlists.
 Mentor fresh graduate engineers with the design flow, strategy.
Qualification
 Strong Verilog, Synopsys DC/PT/ICC, C/C++, Perl/shell scripts or Vera programming skills.
 Must have good leadership/communication skills.
 Networking experience is highly desirable, but not required.
 Track record of successfully design of ASIC’s from start to finish.

ASIC Verification Engineer
Job Summary:
 Perform ASIC verification for large, complex high-speed ASIC’s for Juniper’s next generation of networking products.
 Responsible for block as well as fullchip/multichip verification
 Responsibilities
 Develop detailed test plans, block and system-level test benches and verification environments; execute and achieve complete coverage to ensure first working silicon.
 Develop functional models for architectural validation.
 Need to meet or exceed test-plan/chip schedule.
 You will work closely with logic designers to resolve bugs, software developers to assist in software and bring-up development.
 Mentor junior engineers with the verification flow, strategy.
 Develop Perl, Tcl and/or shell scripts to enhance current verification infrastructure/methodology.
Qualification
 Strong Verilog, SystemC or C/C++, Perl/shell scripts or Vera programming skills.
 Must have good leadership/communication skills.
 Networking experience is highly desirable, but not required.
 Track record of successfully delivered multiple ASIC’s from start to finish.

Pls feel free to mail me should you need any further clarification.

Thanks
Shantonu Ghosh
Juniper Networks | Recruiting Specialist
Email shantonu@juniper.net
LinkedIn http://www.linkedin.com/in/shantonu