DV Synapse Design

DV Synapse Design mike@synapse-da.com p

Bangalore

Design Verification

Create verification plans for SoC level verification

Create testbenches in C/C++

Utilize advanced verification techniques

Write tools and scripts in Perl and other script languages to enhance the verification process

Qualifications and requirements:

BS, MS, PhD, in computer science or engineering

Working knowledge of ARM-based processors and AMBA bus protocols

Experience with simulators from one or more of the major EDA suppliers (Cadence, Mentor or Synopsys)

Working knowledge of Verilog

Experience with tools for regression management, configuration management and bug tracking

Good problem solving and debugging skills

Qualifications: BS or MS

Experience: 4 to 12 yrs

nSys – Verification Engineers

nSys hiring Verification Engineers Delhi Experience: 3 – 6 yrs Skills: Should be proficient in SystemVerilog OVM/VMM, AMBA/USB/PCIe/Ethernet/SAS/SATA protocol knowledge desirableInterested candidates, please send your CV to shilpa.verma@nsysinc.com

Sr. Design Verification Engineer

Location: Xilinx India, Hyderabad

Contact: ravikir@xilinx.com
Detailed Description

Xilinx has a position for Senior Design Verification Engineer. The candidate for this position will architect and implement simulation verification environment, flows and infrastructure. Successful candidate will have proficiency in developing advanced verification flows.
The candidate will have an opportunity to help create reusable verification environments to be used across multiple projects.
The role involves VLSI functional verification including
• Developing coverage driven verification methodologies and flows
• Developing and implementing simulation and debug flows
• Developing functional coverage and coverage analysis environment
• Writing tools and scripts in Perl and other script languages to enhance the verification process
• Evaluating industry leading tools for use in design verification.
• Technical Leadership role including mentoring other engineers.

Job Requirements

BS/MS in EE, Computer Engineering, or equivalent field.
Strong Software programming background
Strong verification background and proven experience in architecting and implementing verification tools and flows. Strong programming skills in Verilog and hardware verification languages (HVLs) such as SystemVerilog, Vera or Specman ‘e’.
Programming skill and experience in one or more of C, C++ and perl is a strong plus. Comfort with a diversity of programming environments and tools. Experience with a reuse methodology/class library, such as VMM, OVM, RVM. Experience with Oriented Programming (OOP) techniques
Experience with developing verification tools like random code generators, regression management tools and automation of verification is highly desirable

Staff Design Verification Engineer (Manager / Sr Manager – Central Verification Methodology Team)

Location: Xilinx India, Hyderabad;

Contact: ravikir@xilinx.com
Detailed Description:
Xilinx has a position for Staff Design Verification Engineer. The candidate for this position will architect and implement Test Benches, including random environment, error generation, checkers and monitors. Successful candidate will have proficiency in efficiently developing advanced verification environments. The candidate will have an opportunity to help create reusable verification environments to be used across multiple projects.
The role involves VLSI functional verification including
• Developing coverage driven verification envirnoments
• Developing and implementing verification plans
• Creating assertions with SystemVerilog (SVA) and verifying using static tools or simulator
• Developing functional coverage and coverage analysis
• Developing simulation infrastructure and debug environments.
• Writing tools and scripts in Perl and other script languages to enhance the verification process
• Evaluating industry leading tools for use in design verification.
• Technical Leadership role including mentoring other engineers.

Job Requirements:
• 12+ yrs of Relevant experience with BS/MS in EE, Computer Engineering, or equivalent field.
• Strong verification background and proven experience in architecting and implementing comprehensive test benches. Strong programming skills in Verilog/VHDL and hardware verification languages (HVLs) such as SystemVerilog, Vera or Specman ‘e’.
• Programming skill and experience in one or more of C, C++ and perl is a strong plus. Comfort with a diversity of programming environments and tools. Experience with a reuse methodology/class library, such as VMM, OVM, RVM. Experience with Oriented Programming (OOP) techniques
• Experience with developing verification tools like random code generators, regression management tools and automation of verification is highly desired.
• Experience with emulation system and formal verification a plus

Design Verification Engineer

Location: Xilinx India, Hyderabad

Contact: ravikir@xilinx.com
Job Description:
Xilinx is currently looking for a dynamic individual to work within the Processor Solutions and Global Verification Group on the next-generation SOC ASIC design. The individual will manage and contribute to the architecture and implementation of the verification testbench using System Verilog and OVM. This individual will work closely with designers to develop a testplan and a stand-alone methodology that is easily portable and reusable within the system testbench. The individual needs to work with teams who are in different geographical areas.
Responsibilities include definition of the verification methodology and the testbench architecture, review of the verification specs, cover groups, and test plans, development of constraint-random stimulus generators, bus-functional models, scoreboards, etc.
Job Requirements

• BS/MS EE, CE, or CS
• 4+ years of design verification experience
• 2+ years of OOP coding experience (VERA, System Verilog, SpecmanE or C++) and SV Assertions
• Strong Familiarity with Verification Methodologies such as OVM, AVM, or VMM
• Familiarity with Verilog and General Logic Design concepts
• Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR2/DDR3, and peripherals such as USB and Ethernet
• Strong working knowledge of UNIX environment and scripting languages such as Perl or Python
• Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim
• Experience using UNIX Revision Control tools – Subversion, RCS, CVS, Perforce and bug tracking tools such as Bugzilla
• Experience in verifying multimillion gate chip designs from specifications to tape-out
• Excellent communication and presentation skills
• Excellent leadership and project management skills
• Demonstrate the ability to work with cross-functional teams
• Familiarity with processors and SOC Debug architectures such as Coresight is a plus
• Familiarity Software development flow including assembly and C is beneficial

nSys hiring Verification Engineers (Delhi)

Position: Sr Verification Engineer
Job Location: Delhi
Experience: 3 – 6 yrs
Skills: Should be proficient in SystemVerilog (OVM/VMM), AMBA/USB/PCIe/Ethernet protocol knowledge desirable

Interested candidates, please send your CV to jp@nsysinc.com

Freshers

Infotech Enterprises Limited, Hyderabad

Looking for ME/M.Tech/MS – Mechanical / Aeronautical / VLSI / Power Systems (2009/10 pass outs only)

Eligibility:
Fresh Post Graduates (Mechanical / Aeronautical / VLSI / Power Systems), who have completed in the year 2009/2010 with an aggregate of 60% are eligible.

Walk-in Date & Time: 29th August ’10 (Sunday) @ 9:00AM

Note: Spot Registration will be done at the Venue up to 10AM on 29th Aug. (Sunday).

Candidates have to carry the following documents:
All academic credentials (xerox copies), Photo ID proof (License / Passport / College ID card) , Latest Resume, Two Passport size photographs.

Venue: Infotech Enterprises Limited, Plot No.11, Software Units Layout, Infocity, Madhapur, Hyderabad. Telephone: 040 – 23110357 / 8, http://www.infotech-enterprises.com

Selection Process:

1. Written Tests: 29th August’10 (Sunday)
a. Aptitude Test (Duration: 50 minutes)
Quantitative Aptitude, Verbal Ability, Reading Comprehension, Data Interpretation

b. Technical Test (Specific to engineering discipline)- Duration: 60 minutes

Mechanical / Aeronautical: Strength of Materials, Machine Design, Theory of Machines, Composits, Thermo dynamics & Heat transfer.

VLSI: CMOS fundamentals, Number Systems, Digital Design, Combinational Logic, Sequential Logic, Shift registers, counters

Power Systems: Fundamental of Power Systems and Electrical Engineering.

2. Technical & HR interviews: 30th August’10 (those who clear in Written Test)
3. Any further information will be provided by the helpdesk at the registration center.

Terms & Conditions of Employment:

1. Designation: Assistant Design Engineer / Software Engineer Trainee.
2. Compensation Package: 2.2 Lakh Per Annum.

3. Service Commitment: Two Years from Date of Joining.

4. Selected candidates should be available to join immediately.

5. Job Location: Hyderabad.

Note: Eligible candidates can walk-in directly on 29th Aug’10. Out station candidates have to make their own arrangements for Travel & Stay and they should be prepared to stay till Monday / Tuesday (30th / 31st Aug’10) in case if it is required.
Best Regards,

Recruitment Team.

Infotech Enterprises Limited, Hyderabad.

URL: http://www.infotech-enterprises.com

SystemC & TLM modeling standard Engineers Immediately for Texas Instruments Bangalore

Dear ,

Currently we have a Immediate Opening in Texas Instruments Bangalore Based Company , Your Profile is exactly matching to the requirements, So kindly send ur Updated Cv & Ur CTC Details ASAP for further Processings.

Requirement: Software Systems Engineer

Knowledge of modeling & simulation technologies.

Specifically, the below will be considered as preferred:
1. SystemC & TLM modeling standard
2. Instruction set simulation
3. Compiler, code translation technology
4. Embedded systems chip architecture
5. DSP – architecture and basic idea of algorithms
6. VLSI design overview
7. Hardware design language (VHDL/Verilog) overview
8. Java, Javascripting
9. Eclipse environment
10. Multicore programming

Primary and Secondary Responsibilities:

1. Develop the OMAP5/6 TPIC system model
2. Contribute to several system modeling projects, infrastructure and technology development

Complex Tasks:

1. Understand TPIC system architecture, map out modeling requirements.
2. Develop a plan by reviewing the software needs, assessing reusable modeling pieces available with arch team, etc
3. Design and implement a reusable framework
Management/Organizational Skills: (covered by the above)
Mostly one of coordinating the model development with the system arch team, internal staff and with software teams (who are the users)

Team and People Skills: Just be a great team player, manage dependencies within the team and work to resolve them
Projects and Deliverables:
TPIC system model development tracking and delivery

Exp:——–3+yrs.

Thanks & regards

Shankar.

E-mail :- shankar@connectprosearch.com;shankarsuri2007@gmail.com

Leading DESIGN MNC in Bangalore Needs experts in SoC/RTL Design/Verification.

Interested candidates please see details below. Email
your resume at ruchi@cmctechjobs.com/ 09811026286.
1. RTL Design Engineer/Lead

This role involves:
Driving integration and micro-architecture of complex SoCs, based on
Centaurus/OMAP platforms
Participating and driving key aspects of specification (e.g clocking,
power management, interconnect, etc)
Opportunity in micro-architecture and architecture innovation, leading
Playing significant role in driving timing constraints and closure of
core as well as interface timing
Working with tool vendors and driving methodology aspects
Managing IP dependencies, planning and tracking of all RTL tasks
Opportunity to build and manage a new team

Qualifications:
6-10 years of experience in SoC RTL design
Must me well versed with micro architecture and integration aspects
of complex SoCs
Familiar with HL0.8 architecture
Solid understanding of power management, security, emulation aspects
Good understanding of key IPs (PRCM, Debug-SS, L3/L4 interconnect
IP)
Good understanding of DV and DFT domains
Good understanding of STA

Preferred additional skills
Knowledge of synthesis and key physical design care abouts
AutoGen environment

1. DV Lead

This role involves:
Leading & owning the complete verification of complex SoCs based on
Centaurus/OMAP platforms
Participation in SoC specification, working closely with architecture
and marketing
Task assignment, Planning & tracking
Working with tool vendors and driving methodology aspects
May include managing IP verification of chip infrastructure IPs
(interconnect, power management, etc) and other strategic IPs
Opportunity to build and manage a new team

Job Qualifications:
6-10 years of experience in SoC DV
Solid understanding of design verification concepts at IP & SoC
level
Good understanding of RTL and SoC integration
Expertise in SoC verification, starting from test plan creation to
complete execution for RTL & gate level.
Solid understanding of complex SoC architecture
Good understanding of key IPs and chip infrastructure like
power-mgmt, security, emulation for SoCs like OMAP or Centaurus.
Experience in post-silicon (e.g TDL, tester, bench si-validation,
etc) debug/support

Preferred additional skills
Understanding of OMAP/DaVinci architecture
Exposure to power aware verification
Experience in IP verification
Experience in Palladium/FPGA

Application Validation & Verification Engineer/Lead

This role involves:

Leading & owning the complete Application Validation of complex SoCs
based on Centaurus/OMAP platforms
Participation in SoC specification, working closely with architecture,
SW architecture and marketing.
Working closely with Design team, SW drivers team, codecs team and
other SW teams
Driving definition of pre and post silicon validation platforms by
working with cross-functional teams.
Customer support – collaterals/documentation, technical support (si
bringup, providing basic training on TI devices, answering technical
questions)
Re-produce/Debug silicon issues on TI platforms (VDB etc.)
Support Si bring-up activities
Bench characterization of new devices (on specific need basis)
Task assignment, Planning & tracking
Opportunity to build and manage a new team
Supervisory responsibilities

Qualifications:

6-10 years of experience in AV&V or SW validation
Solid understanding of system verification concepts at IP & SoC
level
Expertise in system verification, starting from test plan creation
to complete execution for complex use cases.
Solid understanding of complex SoC architecture
Good understanding of key IPs and chip infrastructure like
power-mgmt, security, emulation.
Experience in hardware board debug
Experience in post-silicon system verification
Good knowledge of C

Preferred additional skills
Understanding of OMAP/DaVinci architecture
Experience in Palladium/FPGA
Experience in IP verification
Experience of using RTOS

QLogic – Pune

There are openings with QLogic – Pune (www.qlogic.com) for ASIC Design & Verification Engineer.if any one is interested please send me your profile to dipesh1120@gmail.com

QLogic simplifies the process of networking storage by providing easy to use high performance SAN products of exceptional quality. QLogic produces the controller chips, host bus adapters (HBA’s), fabric switches and management software that are the backbone of storage networks for most Global 2000 corporations as well as small and medium businesses. QLogic builds solutions based on all storage network technologies including SCSI, iSCSI, Inifiband, FCoE and Fibre Channel.
We are currently looking for an ASIC Design Engineer at our Pune facility in India.

Please check below JD

ASIC Design Engineer (8+)

Job responsibilities include:
• Design blocks of logic using Verilog or VHDL hardware languages
• Analyze functional specifications and test plans in order to develop unit simulation test benches for ASIC verification
• Investigate performance improvements
This position requires independent thinking to resolve issues associated with the design and test of complex ASICs. In addition, the job requires approaching design and problem resolution with exacting precision and attention to detail to continue a strong history of first pass success. All tasks are completed in a team environment using state of the art simulation and analysis tools.

EDUCATION
BS or MS degree in Electrical Engineering, Computer Engineering or related discipline

REQUIRED EXPERIENCE
10 to 15 years of experience working in ASIC design related to storage, networking or high-performance computing domain.
Completed a PCI Express or Ethernet design project
Exposures to 10Gb Ethernet, PCI Express, Fibre Channel or Infiniband would be an added advantage.
Experience with Palladium preferred.

REQUIRED SKILLS:
Fluent in Verilog with exposure to System Verilog.
Excellent written & verbal communications skills.
TCL/shell scripting experience Storage and Ethernet Industry experience preferred.
Cadence NCsim

ASIC Verification Engineer(8+)

Job responsibilities include:
• Analyze functional specifications and test plans in order to develop unit simulation test benches for ASIC verification
This position requires independent thinking to resolve issues associated with the design and test of complex ASICs. In addition, the job requires approaching design and problem resolution with exacting precision and attention to detail to continue a strong history of first pass success with multiple tape-outs. All tasks are completed in a team environment using state of the art simulation and analysis tools.

EDUCATION
BS or MS degree in Electrical Engineering, Computer Engineering or related discipline

REQUIRED EXPERIENCE
12 TO 15 years of experience working in ASIC verification.
Completed a PCI Express verification project
Experience implementing directed and random test cases.
Experience developing and using system/block level complex test benches as well as writing verification plans and requirements.
Understand verification methodologies for complex ASIC designs.
Experience in creating test plan, writing test cases and debugging logic.
Experience integrating and verifying externally developed IP’s.
Experience with mixed RTL/DV, assertion, formal verification and code coverage.
Exposures to 10Gb Ethernet, PCI Express (PCIe), Fibre Channel, Infiniband protocols
Experience with Palladium is an added advantage

REQUIRED SKILLS:
Fluent in Verilog with exposure to System Verilog.
Excellent written & verbal communications skills.
TCL/shell scripting experience Storage and Ethernet Industry experience preferred.
Cadence NCsim
Experience with product companies in storage, networking and/or high-performance computing space would be preferred.