Staff Design Verification Engineer (Manager / Sr Manager – Central Verification Methodology Team)

Location: Xilinx India, Hyderabad;

Contact: ravikir@xilinx.com
Detailed Description:
Xilinx has a position for Staff Design Verification Engineer. The candidate for this position will architect and implement Test Benches, including random environment, error generation, checkers and monitors. Successful candidate will have proficiency in efficiently developing advanced verification environments. The candidate will have an opportunity to help create reusable verification environments to be used across multiple projects.
The role involves VLSI functional verification including
• Developing coverage driven verification envirnoments
• Developing and implementing verification plans
• Creating assertions with SystemVerilog (SVA) and verifying using static tools or simulator
• Developing functional coverage and coverage analysis
• Developing simulation infrastructure and debug environments.
• Writing tools and scripts in Perl and other script languages to enhance the verification process
• Evaluating industry leading tools for use in design verification.
• Technical Leadership role including mentoring other engineers.

Job Requirements:
• 12+ yrs of Relevant experience with BS/MS in EE, Computer Engineering, or equivalent field.
• Strong verification background and proven experience in architecting and implementing comprehensive test benches. Strong programming skills in Verilog/VHDL and hardware verification languages (HVLs) such as SystemVerilog, Vera or Specman ‘e’.
• Programming skill and experience in one or more of C, C++ and perl is a strong plus. Comfort with a diversity of programming environments and tools. Experience with a reuse methodology/class library, such as VMM, OVM, RVM. Experience with Oriented Programming (OOP) techniques
• Experience with developing verification tools like random code generators, regression management tools and automation of verification is highly desired.
• Experience with emulation system and formal verification a plus