Mirafra Technologies Bangalore

1) Verification :

Very good knowledge of System Verilog

Should have worked on Complex Module/SOC level verification

Exp : 2 to 8 years

2) SoC /CPU subsystem verification

Experience in SoC /CPU subsystem verification

Familiarity with ARM, AHB, AXI, APB protocols

SystemVerilog expertise

DMA/Switching knowledge is desirable

Exp : 2 – 8 years of strong experience in DV

3 ) STA/Synthesis with extensive DC/PT exposure

Overall experience – 2 to 8 years relevant experience

4) Complex verification, SV, Networking Exp : 2 – 8 years

Kindly send ur Resumes to E-mail :- shankar@connectprosearch.com:shnakrsuri2007@gmail.com

Weekend Interviews – System Verilog expertise – Noida –

3 yrs – 6 yrs – KPIT Cummins Infosystems Ltd.
Hi,

We are looking for many engineers for our Noida centre with System Verilog language expertise.

Any methodology knowledge like OVM, VMM, AVM will be an added advantage.

Exp: 3 yrs – 6 yrs
Location: Noida

Please revert with your resume to me asap for further process.

Gargi Dave
gargi.dave@kpitcummins.com

KPIT Cummins Infosystems Ltd.

Brocade – Bangalore

Job Title: Senior ASIC verification engineer
Requisition #: 3984
Function: Engineering
Country: India
State: Karnataka
City: Bangalore
Travel Requirements: Up to 25%
Position Type: Employee
Position Level: Professional
Job Description: Day-to-Day Responsibilities

• Develop test bench using System Verilog
• Develop test cases and do full chip verification
• Design using RTL and perform timing analysis

Qualifications/Job Responsibilities: • Working knowledge of networking protocols
• Experience with verilog RTL coding
• Experience in ASIC methodologies and tools (synthesis, timing and formal verification)
• Experience in C++, System verilog and scripting languages like PERL

• BE/B.Tech in EE/CS and about 7yrs experience in ASIC development

Brocade – Bangalore

Job Title: Lead ASIC Verification
Requisition #: 3370
Function: Engineering
Country: India
State: Karnataka
City: Bangalore
Travel Requirements: Up to 25%
Position Type: Employee
Position Level: Professional
Job Description: Lead ASIC Verification Engineer

Responsibilities:
* Develop full chip and block level test bench in C++ and System Verilog environment.
* Define test plan and verification methodology.
* Technically lead the team for developing full chip test bench and verification.

Qualifications/Job Responsibilities: * Experience in System Verilog or an equivalent verification language
* Working knowledge of Network protocols(Ethernet/IP/TCP)
* Experience in ASIC methodologies and tools (synthesis, timing and formal verification)
* Experience in C++, System verilog and scripting languages

* BSEE/CS with 8+ years of experience

Looking for Application Consultant to be based out of Hyderabad

Job Responsibilities:

Verification is the number one bottleneck in SOC designs today. Synopsys is uniquely positioned to offer the most complete verification solution in market today. VCS is the Platform for Synopsys verification flow. It incorporates a suite of built-in high performance next generation technologies for test bench automation, assertion based verification, coverage closure, etc., which are needed for verifying challenging multi-million gate designs.
Verification AC’s have the opportunity to work with various customers, giving them abundant exposure to different design styles and verification methodologies that are being used in the industry today. He/She partners with customers on training, problem resolution, methodology guidance, and technical account management. He/She is expected to manage multiple customer issues concurrently and be very effective at interacting with customers, not only verification/design engineers, but first or second level management as well. The verification AC works with Synopsys Sales Team on product demonstrations, evaluations, and competitive benchmarking. He/She plays an active role in account planning, working as part of the account team to develop solutions to customer problems based on their insight into the customers’ needs and issues. Verification AC’s are part of an AC team managed by the Technical Manager. They also provide technical feedback to Synopsys product development teams pertaining to issues that customers face in the field, what’s working/not working, recommended enhancements etc. This position allows the individual to learn the state-of-art verification flows/methodology from Synopsys as well as hone his/her leadership skills in driving technology campaigns.

Job Requirements:

BS/MS with 5+ years of relevant experience. Good knowledge of high-level design methodologies and strong communication skills are required. Ability to work with customers and CAE/R&D teams is important. Proficient with Unix, HDL (Verilog/VHDL), Gate Level Verification, Debugging, HVL(e/vera/systemverilog) and a strong understanding of ASIC design flows, VLSI, and/or CAD-engineering. He/She should possess excellent customer interface, negotiation, communication and planning skills. He/she should have the ability to lead and manage complex tasks to achieve timely completion consistent with program schedule and cost constraints.

Location: Hyderabad

Interested candidates can send their profiles to sarni@synopsys.com

IP Verification Engineer : 6 to 10 years : Specman-e verification : Infineon Bangalore

Mandatory:
B.Tech/M.Tech in EE/EC from a reputed institution.
6 to 10 years of industry experience
Proficiency in Specman –e , System Verilog, VHDL , Verilog , C/C++ and Perl is a must.
Expertise in functional verification and debugging of ASIC / VLSI Designs using Specman-e verification language with a good exposure to EDA Verification tools from Mentor.
Expertise in development of BFMs , Test plan , Test cases and Vmanager Flow.
Hands on experience in developing and debugging Score boards , preferably with ARM processors, eVCs and dealing with c/c++ reference models.
Knowledge on code coverage and functional coverage analysis is essential.
Must have actively participated in a Complex SoC / IP Verification Team either at block level or top level using Specman.
Familiarity with System C and participation in specman verification of a reference model written in C/C++/System C will be an added advantage.

Preferred:

Experience with Unix and Windows-XP development environments
Familiarity with System Verilog at least in one major IP / SOC verification will be an added advantage.
Familiarity with Configuration management Systems, preferably Clearcase.
Good understanding of Microprocessor, Microcontrollers, SoC architecture, bus protocols -particularly AMBA AHB, wireless baseband related peripherals, etc.
A proactive team player with good written and verbal communication skills

Require for current open requisitions in Virage Logic – Noida, Pune & Bangalor

Lead Design Arbiter (Pune)

· Lead the end to end development and productization of IP cores

· Develop architecture, micro architecture and specifications for IP cores in consultation with marketing and customers

· Articulate the technical value and benefits of our products to customers in the context of the customers’ application.

· Review the design, verification, layout, and all collateral for the product and provide direction to the team to ensure quality and competitiveness

· Take over existing IP core products and manage their development and productization

Requirements:

· In depth knowledge of DDR Controller, arbiter, PHY and related standards is MUST.

· Minimum BS EE/CS required, MS preferred, plus 5 or more years of relevant engineering experience.

· Experience with design of major portions of multiple successful ASIC/SoC designs

· Strong logic design, clock domain crossings, synthesis, functional and timing verification skills

· The ideal candidate will be familiar with all stages in the ASIC design flow including DFT, timing analysis, floor planning, ECO flow, silicon bring-up, and ATE test support.

· Flexible, creative, and able to perform high quality work independently with minimal supervision.

· Team player with excellent written and verbal communications

Experience: Should have at least 5 years experience
Qualification: Minimum BS EE/CS required, MS preferred

Require for current open requisitions in Virage Logic – Noida, Pune & Bangalore

Verification Engineer (Pune)

As a Verification Engineer you would develop test plan from specification, design verification infrastructure and execute exhaustive logic verification. Specific application areas include MIPI controller and PHY.
In this position you will be responsible for Verification driver, monitor and score-board development, Test case development, Logic verification and assist the design team to fix bugs.

Requirements:

· Bachelors or Masters degree in electronics or electrical engineering (BSEE or MSEE) or equivalent from reputed universities with over 5 years experience in design verification

· Using scripting languages, design System Verilog based simulation test benches, writing PLI routines and running simulations

· Experience with System Verilog and/or Specman test languages and formal verification tools

· Experience in developing constrained random based test environments

· Excellent analysis and debugging skills.

· Good communication and interpersonal skills and team player.

Experience: Should have at least 4 years experience
Qualification: Minimum BS EE/CS required, MS preferred

Require for current open requisitions in Virage Logic – Noida, Pune & Bangalore

3. Lead Design Engineer/Manager (Bangalore)

· Responsible for development of a complete of SoC design flow

· Good understanding of all aspects of design flow development, including Logic verification, Synthesis, STA, SSTA, Place & Route, CTS, PNS, LVS/DRC etc

· Need the ability to mentor and guide junior engineers.

Requirements:

· In depth knowledge of end to end SOC/ASIC flow in submicron process nodes..

· Minimum BS EE required, MS preferred, plus 8 or more years of relevant chip design experience.

· Experience in resource and task management of design, verification and physical design teams

· Experience with design of major portions of multiple successful ASIC/SoC designs

· Strong logic design, synthesis, functional and timing verification skills Experience with design of major portions of multiple successful ASIC/SoC designs

· The ideal candidate will be familiar with all stages in the ASIC design flow including DFT, timing analysis, floor planning, ECO flow, STA, Silicon bring up flow

· Flexible, creative, and able to perform high quality work

· Good communication, interpersonal skills, team motivator and team player

Experience: Should have at least 8 years experience
Qualification: Minimum BS EE/CS required, MS preferred

Require for current open requisitions in Virage Logic – Noida, Pune & Bangalore

2. Group Leader/Manager – IQA (Noida)

Work as the team leader of the corporate quality team to enforce existing quality standards and develop new ones for semiconductor IP products

Requirements:
· Very good understanding of how VLSI circuits work and be able to detect design issues during QA process and communicate to designers.

· Be able to develop automation tools to improve efficiency.

· Familiar with most EDA tools for COT design flow: simulation, synthesis, STA, P&R and physical verification.

· 8+ years working experience in VLSI design fields. EE/EECS degrees in VLSI required at either BS or MS level.

· VLSI layout skill is a big plus for this position.

· Need the ability to mentor and guide junior engineers

As part of the shipping team you will have the following responsibilities:
· follow product release procedure.

· Develops, analyzes and maintains tools that support and automate processes for hardware or software product release.

Experience: Should have at least 8+ years experience
Qualification: EE/EECS degrees in VLSI required at either BS or MS level