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Design Verification Engineer

Posted by verification job on August 30, 2010

Location: Xilinx India, Hyderabad

Contact: ravikir@xilinx.com
Job Description:
Xilinx is currently looking for a dynamic individual to work within the Processor Solutions and Global Verification Group on the next-generation SOC ASIC design. The individual will manage and contribute to the architecture and implementation of the verification testbench using System Verilog and OVM. This individual will work closely with designers to develop a testplan and a stand-alone methodology that is easily portable and reusable within the system testbench. The individual needs to work with teams who are in different geographical areas.
Responsibilities include definition of the verification methodology and the testbench architecture, review of the verification specs, cover groups, and test plans, development of constraint-random stimulus generators, bus-functional models, scoreboards, etc.
Job Requirements

• BS/MS EE, CE, or CS
• 4+ years of design verification experience
• 2+ years of OOP coding experience (VERA, System Verilog, SpecmanE or C++) and SV Assertions
• Strong Familiarity with Verification Methodologies such as OVM, AVM, or VMM
• Familiarity with Verilog and General Logic Design concepts
• Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR2/DDR3, and peripherals such as USB and Ethernet
• Strong working knowledge of UNIX environment and scripting languages such as Perl or Python
• Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim
• Experience using UNIX Revision Control tools – Subversion, RCS, CVS, Perforce and bug tracking tools such as Bugzilla
• Experience in verifying multimillion gate chip designs from specifications to tape-out
• Excellent communication and presentation skills
• Excellent leadership and project management skills
• Demonstrate the ability to work with cross-functional teams
• Familiarity with processors and SOC Debug architectures such as Coresight is a plus
• Familiarity Software development flow including assembly and C is beneficial

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