Sr. Design Verification Engineer
Posted by verification job on August 30, 2010
Location: Xilinx India, Hyderabad
Xilinx has a position for Senior Design Verification Engineer. The candidate for this position will architect and implement simulation verification environment, flows and infrastructure. Successful candidate will have proficiency in developing advanced verification flows.
The candidate will have an opportunity to help create reusable verification environments to be used across multiple projects.
The role involves VLSI functional verification including
• Developing coverage driven verification methodologies and flows
• Developing and implementing simulation and debug flows
• Developing functional coverage and coverage analysis environment
• Writing tools and scripts in Perl and other script languages to enhance the verification process
• Evaluating industry leading tools for use in design verification.
• Technical Leadership role including mentoring other engineers.
BS/MS in EE, Computer Engineering, or equivalent field.
Strong Software programming background
Strong verification background and proven experience in architecting and implementing verification tools and flows. Strong programming skills in Verilog and hardware verification languages (HVLs) such as SystemVerilog, Vera or Specman ‘e’.
Programming skill and experience in one or more of C, C++ and perl is a strong plus. Comfort with a diversity of programming environments and tools. Experience with a reuse methodology/class library, such as VMM, OVM, RVM. Experience with Oriented Programming (OOP) techniques
Experience with developing verification tools like random code generators, regression management tools and automation of verification is highly desirable