Verification Manager,Sr Verification Engineers(10+yrs) in large semicon, Blr
1. Verification Manager Req
Job Requirement:
· MSEE with 10+ years or BS with 12+ years in chip design and verification.
· Experience in managing 2 to 5 engineers.
· Worked in the US or a US based company in India for 5+ years.
· Should have worked as an individual contributor in an ASIC verification background for 5 years.
· Experience in verification lead position.
· Experience in planning the verification process, resource allocation and creating realistic schedule estimates.
· Experience in developing coverage-driven verification test plans.
· Experience writing test specifications (plans) and creating directed and random test cases.
· Experience managing regression analysis
· Experience in high level Object Oriented test bench environments such as VMM/UVM .
· Strong System Verilog, PERL, TCL, and C/C++ programming skills
· Experience in planning the verification process and coming up with realistic schedule estimates.
· Able to adopt the use of new techniques and methodologies and promote their use within the project.
· A high level of pro-activity, initiative and problem solving.
· Familiarity with constrained random and assertion based verification is preferred
· Verification experience in SERDES, Ethernet Networking in Verilog is a big plus.
· Knowledge of SONET and IEEE 802.3 Physical layer clauses is a plus.
2. Sr Verification Engineers Req
Job Requirement:
· MSEE with 10+ years or BS with 12+ years in chip design and verification.
· Worked in the US or a US based company in India for 5+ years.
· Should have worked as an individual contributor in an ASIC verification background for 5 years.
· Experience in verification lead position.
· Experience in planning the verification process and creating realistic schedule estimates.
· Experience in developing coverage-driven verification test plans
· Experience writing test specifications (plans) and creating directed and random test cases.
· Experience managing regression analysis
· Experience in high level Object Oriented test bench environments such as VMM/UVM .
· Strong System Verilog, PERL, TCL, and C/C++ programming skills
· Experience in planning the verification process and coming up with realistic schedule estimates.
· Able to adopt the use of new techniques and methodologies and promote their use within the project.
· A high level of pro-activity, initiative and problem solving.
· Familiarity with constrained random and assertion based verification is preferred
· Verification experience in SERDES, Ethernet Networking in Verilog is a big plus.
· Knowledge of SONET and IEEE 802.3 Physical layer clauses is a plus.
For more information: jabeena.m@alpconsulting.in
Mobile: 9538716955