RTL Design Openings ( ASIC ), Exp Level 3 ~ 7 YrsExp, in Bangalore.

For more details, Email Me: rahman.a@alpconsulting.in;

I shall revert back to you with client details..

RTL design preferably with communication & Storage domain

Design Exp in Ethernet MAC, PCS domain for 100G, 40 G MAC and PCS layer

Design Exp in SONET for Generic framing protocols (GSP,GBP) upto 100 Ghz

Design Exp in CPU subsystems at block level, system bus level with peripherals like DMA controllers

Design Exp on High speed Packet interfaces

Design exp on OTM (Optical transport Mechanism)

Design engineers must be confident on High speed ,complex IP’s at 65nm and 40 nm nodes. They should understand asynchronous protocols and multiclock domains